Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Bedienungsanleitung PDF herunterladen (Seite 138)

Distributed Clocks SYNC/LATCH Signals

III-126 Slave Controller – IP Core for Xilinx FPGAs

11 Distributed Clocks SYNC/LATCH Signals

For details about the Distributed Clocks refer to Section I.

11.1 Signals

The Distributed Clocks unit of the IP Core has the following external signals (depending on the ESC

configuration):

EtherCAT

device

LATCH_IN0

SYNC_OUT1

SYNC_OUT0

LATCH_IN1

Figure 63: Distributed Clocks signals

Table 64: Distributed Clocks signals

Signal

Direction

Description

SYNC_OUT0/1

OUT

SyncSignals (alias SYNC[1:0])

LATCH_IN0/1

LatchSignals (alias LATCH[1:0])

NOTE: SYNC_OUT0/1 are active high/push-pull outputs.

11.2 Timing specifications

Table 65: DC SYNC/LATCH timing characteristics IP Core

Parameter

Min

Max

Comment

DC_LATCH

12 ns + x

Time between Latch0/1 events

DC_SYNC_Jitter

11 ns + x

SYNC0/1 output jitter

DC_SYNC_IRQ_pulse_width

40 ns

SYNC0/1 pulse width if the SYNC0/1

signal is used as AL event request (PDI

interrupt) signal (masked by register

0x0220 ff.), and if acknowledge mode is

not used.

LATCH0/1

DC_LATCH

Figure 64: LatchSignal timing

SYNC0/1

DC_SYNC_Jitter

Output event time

DC_SYNC_Jitter

Figure 65: SyncSignal timing

EtherCAT IP Core: time depends on synthesis results

1 2 ... 133 134 135 136 137 138 139 140 141 142 143 144

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