Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Bedienungsanleitung PDF herunterladen (Seite 95)

Ethernet Interface

Slave Controller – IP Core for Xilinx FPGAs III-83

Table 39: MII TX Timing characteristics

Parameter

Comment

CLK25

25 MHz quartz oscillator (CLK_IN)

TX_delay

MII_TX_ENA/MII_TX_DATA[3:0] delay after rising edge of CLK_IN,

depends on synthesis results

PHY_TX_CLK

Delay between PHY clock source and TX_CLK output of the PHY,

PHY dependent

PHY_TX_setup

PHY setup requirement: TX_ENA/TX_DATA with respect to TX_CLK

(PHY dependent, IEEE802.3 limit is 15 ns)

PHY_TX_hold

PHY hold requirement: TX_ENA/TX_DATA with respect to TX_CLK

(PHY dependent, IEEE802.3 limit is 0 ns)

If the phase shift between CLK25 and TX_CLK should not be constant for a some special PHYs,

additional FIFOs for MII_TX_ENA/MII_TX_DATA are necessary. The FIFO input uses CLK25, the

FIFO output TX_CLK[0] or TX_CLK[1] respectively.

NOTE: The phase shift can be adjusted by displaying TX_CLK of a PHY and MII_TX_ENA/MII_TX_DATA[3:0] on

an oscilloscope. MII_TX_ENA/MII_TX_DATA[3:0] is allowed to change between 0 ns and 25 ns after a rising

edge of TX_CLK (according to IEEE802.3 – check your PHY’s documentation). Setup phase shift so that

MII_TX_ENA/MII_TX_DATA[3:0] change near the middle of this range. MII_TX_ENA/MII_TX_DATA[3:0] signals

are generated at the same time.

9.2.3 MII Timing specifications

Table 40: MII timing characteristics

Parameter

Min

Typ

Max

Comment

RX_CLK

40 ns ± 100 ppm

RX_CLK period (100 ppm with maximum FIFO

Size only)

RX_setup

RX_DV/RX_DATA/RX_D[3:0] valid before rising

edge of RX_CLK

RX_hold

RX_DV/RX_DATA/RX_D[3:0] valid after rising

edge of RX_CLK

RX_DV

RX_D[3:0]

RX_ERR

RX_CLK

RX_setup

RX_hold

RX signals valid

RX_CLK

Figure 31: MII timing RX signals

EtherCAT IP Core: time depends on synthesis results

1 2 ... 90 91 92 93 94 95 96 97 98 99 100 ... 143 144

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