Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Bedienungsanleitung PDF herunterladen (Seite 6)

CONTENTS

III-VI Slave Controller – IP Core for Xilinx FPGAs

9.1 PHY Management interface 78

9.1.1 PHY Management Interface Signals 78

9.1.2 PHY Address Configuration 78

9.1.3 Separate external MII management interfaces 79

9.1.4 MII management timing specifications 79

9.2 MII Interface 80

9.2.1 MII Interface Signals 81

9.2.2 TX Shift Compensation 82

9.2.3 MII Timing specifications 83

9.2.4 MII example schematic 84

9.3 RMII Interface 85

9.3.1 RMII Interface Signals 85

9.3.2 RMII example schematic 86

9.4 RGMII Interface 87

9.4.1 RGMII Interface Signals 87

9.4.2 RGMII example schematic 89

9.4.3 RGMII RX timing options 89

9.4.4 RGMII TX timing options 89

10 PDI Description 91

10.1 Digital I/O Interface 92

10.1.1 Interface 92

10.1.2 Configuration 93

10.1.3 Digital Inputs 93

10.1.4 Digital Outputs 93

10.1.5 Output Enable 94

10.1.6 SyncManager Watchdog 94

10.1.7 SOF 95

10.1.8 OUTVALID 95

10.1.9 Timing specifications 95

10.2 SPI Slave Interface 98

10.2.1 Interface 98

10.2.2 Configuration 98

10.2.3 SPI access 99

10.2.4 Address modes 99

10.2.5 Commands 100

10.2.6 Interrupt request register (AL Event register) 100

10.2.7 Write access 100

10.2.8 Read access 100

10.2.9 SPI access errors and SPI status flag 101

10.2.10 2 Byte and 4 Byte SPI Masters 102

10.2.11 Timing specifications 103

1 2 3 4 5 6 7 8 9 10 11 ... 143 144

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Bedienungsanleitung Seite 6

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