Beckhoff EtherCAT Technology Section I Bedienungsanleitung

Version 2.2 Date: 2014-07-07 Hardware Data Sheet Section I Slave Controller Section I – Technology EtherCAT Protocol, Physical L

TABLES I-X Slave Controller – Technology TABLES Table 1: ESC Main Features ...

SII EEPROM I-80 Slave Controller – Technology 11.3.3.2 Read Access An EEPROM read access reads 2 or 4 words (4 or 8 bytes, depending on device c

SII EEPROM Slave Controller – Technology I-81 R/W1 001EEPROM_CLKA18EEPROM_DATAtClkA16A17 Ack A15 A13A14 A12 A10A11 A9 AckA8Start Control Byte Hi

Interrupts I-82 Slave Controller – Technology 12 Interrupts ESCs support two types of interrupts: AL Event Requests targeted at a µController, a

Interrupts Slave Controller – Technology I-83 12.2 ECAT Event Request (ECAT Interrupt) ECAT event requests are used to inform the EtherCAT maste

Watchdogs I-84 Slave Controller – Technology 13 Watchdogs The ESCs support up to two internal watchdogs (WD), a Process Data watchdog used for m

Error Counters Slave Controller – Technology I-85 14 Error Counters The ESCs have numerous error counters which help in detecting and locating e

Error Counters I-86 Slave Controller – Technology 14.1 Frame error detection EtherCAT frame error detection takes place at three functional bloc

LED Signals (Indicators) Slave Controller – Technology I-87 15 LED Signals (Indicators) EtherCAT slave controllers support different LEDs regard

LED Signals (Indicators) I-88 Slave Controller – Technology 15.2 ERR LED The ERR LED indicates local errors and application errors. It is either

LED Signals (Indicators) Slave Controller – Technology I-89 15.3 STATE LED and STATE_RUN LED Signal The STATE LED is a bicolor-LED combining RUN

TABLES Slave Controller – Technology I-XI

LED Signals (Indicators) I-90 Slave Controller – Technology 15.5 Port Error LED (PERR) Some ESCs support port receive error indicators PERR(x),

Process Data Interface (PDI) Slave Controller – Technology I-91 16 Process Data Interface (PDI) The Process Data Interface (PDI) realizes the co

Process Data Interface (PDI) I-92 Slave Controller – Technology 16.2 PDI register function acknowledge by write Some ESC functions are triggered

Process Data Interface (PDI) Slave Controller – Technology I-93 16.3 General Purpose I/O Some ESCs support general purpose inputs, outputs, or b

Additional Information I-94 Slave Controller – Technology 17 Additional Information 17.1 ESC Clock Source The initial accuracy of the ESC clock

Additional Information Slave Controller – Technology I-95 17.3 Write Protection Some ESCs are capable of register write protection or entire ESC

Appendix I-96 Slave Controller – Technology 18 Appendix 18.1 Support and Service Beckhoff and their partners around the world offer comprehensi

FIGURES I-XII Slave Controller – Technology FIGURES Figure 1: EtherCAT Slave Controller Block Diagram ...

ABBREVIATIONS Slave Controller – Technology I-XIII ABBREVIATIONS µC Microcontroller ADR Address ADS Automation Device Specification (Beckhoff)

ABBREVIATIONS I-XIV Slave Controller – Technology Cut Through Procedure for cutting directly through an Ethernet frame by a switch before the comple

ABBREVIATIONS Slave Controller – Technology I-XV EPU EtherCAT Processing Unit. The logic core of an ESC containing e.g. registers, memory, and pr

ABBREVIATIONS I-XVI Slave Controller – Technology ISO/OSI Model ISO Open Systems Interconnection Basic Reference Model (ISO 7498): describes the div

ABBREVIATIONS Slave Controller – Technology I-XVII OPB On-Chip Peripheral Bus Optional Service Optional services can be fulfilled by a PROFINET

ABBREVIATIONS I-XVIII Slave Controller – Technology RJ45 FCC Registered Jack, standard Ethernet connector (8P8C) RMII Reduced Media Independent Int

ABBREVIATIONS Slave Controller – Technology I-XIX Subnet Mask Divides the IP address into two parts: a subnet address (in an area separated from

DOCUMENT ORGANIZATION I-II Slave Controller – Technology DOCUMENT ORGANIZATION The Beckhoff EtherCAT Slave Controller (ESC) documentation covers

EtherCAT Slave Controller Overview Slave Controller – Technology I-1 1 EtherCAT Slave Controller Overview An EtherCAT Slave Controller (ESC) tak

EtherCAT Slave Controller Overview I-2 Slave Controller – Technology 1.1 EtherCAT Slave Controller Function Blocks EtherCAT Interfaces (Ethernet

EtherCAT Slave Controller Overview Slave Controller – Technology I-3 Memory An EtherCAT slave can have an address space of up to 64Kbyte. The fir

EtherCAT Protocol I-4 Slave Controller – Technology 2 EtherCAT Protocol EtherCAT uses standard IEEE 802.3 Ethernet frames, thus a standard netwo

EtherCAT Protocol Slave Controller – Technology I-5 2.2 EtherCAT Datagram Figure 3 shows the structure of an EtherCAT frame. Datagram HeaderFCSF

EtherCAT Protocol I-6 Slave Controller – Technology Table 3: EtherCAT Datagram Field Data Type Value/Description Cmd BYTE EtherCAT Command Type (

EtherCAT Protocol Slave Controller – Technology I-7 2.3.1 Device Addressing The device can be addressed via Device Position Address (Auto Increm

EtherCAT Protocol I-8 Slave Controller – Technology 2.4 Working Counter Every EtherCAT datagram ends with a 16 Bit Working Counter (WKC). The Wo

EtherCAT Protocol Slave Controller – Technology I-9 2.5 EtherCAT Command Types All supported EtherCAT Command types are listed in Table 6. For R

DOCUMENT HISTORY Slave Controller – Technology I-III DOCUMENT HISTORY Version Comment 1.0 Initial release 1.1  Chapter Interrupts – AL Event R

EtherCAT Protocol I-10 Slave Controller – Technology Table 6: EtherCAT Command Types CMD Abbr. Name Description 0 NOP No Operation Slave ignores

EtherCAT Protocol Slave Controller – Technology I-11 Table 7: EtherCAT Command Details CMD High Addr. In High Addr. Out Low Addr. Address Match D

Frame Processing I-12 Slave Controller – Technology 3 Frame Processing The ET1100, ET1200, IP Core, and ESC20 slave controllers only support Dir

Frame Processing Slave Controller – Technology I-13 Auto close (manual open) The port is closed depending on the link state, i.e., if the link is

Frame Processing I-14 Slave Controller – Technology 3.2 Frame Processing Order The frame processing order of EtherCAT Slave Controllers depends

Frame Processing Slave Controller – Technology I-15 Example Port Configuration with Ports 0, 1, and 2 If there are only ports 0, 1, and 2, a fram

Frame Processing I-16 Slave Controller – Technology 3.5.1 Unconnected Port 0 Port 0 must not be left intentionally unconnected (slave hardware o

Physical Layer Common Features Slave Controller – Technology I-17 4 Physical Layer Common Features EtherCAT supports two types of Physical Layer

Physical Layer Common Features I-18 Slave Controller – Technology 4.2 Selecting Standard/Enhanced Link Detection Some ESCs distinguish between s

Physical Layer Common Features Slave Controller – Technology I-19 4.3 FIFO Size Reduction The ESCs incorporate a receive FIFO (RX FIFO) for deco

DOCUMENT HISTORY I-IV Slave Controller – Technology Version Comment 1.5  EEPROM Read/Write/Reload example: corrected register addresses  Updated

Ethernet Physical Layer I-20 Slave Controller – Technology 5 Ethernet Physical Layer ESCs with Ethernet Physical Layer support use the MII inter

Ethernet Physical Layer Slave Controller – Technology I-21 5.3 MII Interface Refer to Section III for ESC specific MII information. If an ESC MI

Ethernet Physical Layer I-22 Slave Controller – Technology 5.4 RMII Interface Refer to Section III for ESC specific RMII information. If an ESC

Ethernet Physical Layer Slave Controller – Technology I-23 5.6.2 MI Link Detection and Configuration The EtherCAT IP Core supports link detectio

Ethernet Physical Layer I-24 Slave Controller – Technology 5.8 EtherCAT over Optical Links (FX) EtherCAT communication over optical links using

Ethernet Physical Layer Slave Controller – Technology I-25 5.8.3 ESCs with native FX support ESCs with native FX support have individual PHY res

Ethernet Physical Layer I-26 Slave Controller – Technology 5.10 MII Management Interface (MI) Most EtherCAT slave controllers with MII/RMII/RGMI

Ethernet Physical Layer Slave Controller – Technology I-27 Table 15: PHY Address configuration matches PHY address settings Logical Port Configur

Ethernet Physical Layer I-28 Slave Controller – Technology 5.10.2 Logical Interface The MI of the ESC is typically controlled by EtherCAT via th

Ethernet Physical Layer Slave Controller – Technology I-29 5.10.3 MI Protocol Each MI access begins with a Preamble of “Ones“(32 without preambl

DOCUMENT HISTORY Slave Controller – Technology I-V

Ethernet Physical Layer I-30 Slave Controller – Technology 5.11 MII management example schematic The MII management interface is a shared bus fo

Ethernet Physical Layer Slave Controller – Technology I-31 5.12 Ethernet Termination and Grounding Recommendation This termination and grounding

Ethernet Physical Layer I-32 Slave Controller – Technology 5.13 Ethernet Connector (RJ45 / M12) Fast Ethernet (100BASE-TX) uses two pairs/four p

Ethernet Physical Layer Slave Controller – Technology I-33 5.14 Back-to-Back MII Connection 5.14.1 ESC to ESC Connection Two EtherCAT slave con

Ethernet Physical Layer I-34 Slave Controller – Technology 5.14.2 ESC to Standard Ethernet MAC If an ESC is to be connected directly to a standa

EBUS/LVDS Physical Layer Slave Controller – Technology I-35 6 EBUS/LVDS Physical Layer EBUS is an EtherCAT Physical Layer designed to reduce com

EBUS/LVDS Physical Layer I-36 Slave Controller – Technology 6.2 EBUS Protocol Ethernet/EtherCAT frames are Manchester encoded (Biphase L) and en

EBUS/LVDS Physical Layer Slave Controller – Technology I-37 6.4 Standard EBUS Link Detection Standard EBUS link detection is realized by countin

EBUS/LVDS Physical Layer I-38 Slave Controller – Technology Link disconnection is signaled to the link partner by stopping transmission for a cer

FMMU Slave Controller – Technology I-39 7 FMMU Fieldbus Memory Management Units (FMMU) convert logical addresses into physical addresses by the

CONTENTS I-VI Slave Controller – Technology CONTENTS 1 EtherCAT Slave Controller Overview 1 1.1 EtherCAT Slave Controller Function Blocks 2 1.2

FMMU I-40 Slave Controller – Technology 0 7654321 0 7654321 0 7654321 076Byte 0x00010011Logical Start Address10 7654321 0 7654321 0 7654321 076

SyncManager Slave Controller – Technology I-41 8 SyncManager The memory of an ESC can be used for exchanging data between the EtherCAT master an

SyncManager I-42 Slave Controller – Technology 8.1 Buffered Mode The buffered mode allows writing and reading data simultaneously without interf

SyncManager Slave Controller – Technology I-43 The Status register of the SyncManager reflects the current state. The last written buffer is indi

SyncManager I-44 Slave Controller – Technology The content of an EtherCAT mailbox header is shown in Figure 25. Figure 25: EtherCAT Mailbox Head

SyncManager Slave Controller – Technology I-45 8.5 Single Byte Buffer Length / Watchdog Trigger for Digital Output PDI If a SyncManager is confi

SyncManager I-46 Slave Controller – Technology Master µControllerSlave writes data into mailboxMaster sends mailbox read command Mailbox readSlav

Distributed Clocks Slave Controller – Technology I-47 9 Distributed Clocks The Distributed Clocks (DC) unit of EtherCAT slave controllers suppor

Distributed Clocks I-48 Slave Controller – Technology Propagation Delay The propagation delay between Reference Clock and slave clock has to be t

Distributed Clocks Slave Controller – Technology I-49 9.1.1 Clock Synchronization Process The clock synchronization process consists of three st

CONTENTS Slave Controller – Technology I-VII 5.8.2 Far-End-Fault (FEF) 24 5.8.3 ESCs with native FX support 25 5.8.4 ESCs without native FX

Distributed Clocks I-50 Slave Controller – Technology 9.1.2 Propagation Delay Measurement Since each slave introduces a small processing/forward

Distributed Clocks Slave Controller – Technology I-51 9.1.2.2 Propagation Delay Measurement Example The propagation delay between the local devi

Distributed Clocks I-52 Slave Controller – Technology Slave DSlave FSlave ASlave ESlave CSlave BEtherCAT Processing UnitMasterEtherCAT Processing

Distributed Clocks Slave Controller – Technology I-53 Parameters used for propagation delay calculation are listed in Table 26: Table 26: Paramet

Distributed Clocks I-54 Slave Controller – Technology And for the other direction: tCB = ((tB1 – tB0) – (tC1 – tC0) – tDiff) / 2 Propagation de

Distributed Clocks Slave Controller – Technology I-55 Summary of Propagation Delay Calculation between Slaves tAB = ((tA1 – tA0) – (tB2 – tB0)

Distributed Clocks I-56 Slave Controller – Technology 9.1.4 Resetting the Time Control Loop Before starting drift compensation, the internal fil

Distributed Clocks Slave Controller – Technology I-57 The System Time Difference Filter Depth register (0x0934) and the Speed Counter Filter Dept

Distributed Clocks I-58 Slave Controller – Technology 9.1.6 Reference between DC Registers/Functions and Clocks Table 30: Reference between DC R

Distributed Clocks Slave Controller – Technology I-59 9.1.7 When is Synchronization established? There are two possibilities to detect if DC syn

CONTENTS I-VIII Slave Controller – Technology 9.1.6 Reference between DC Registers/Functions and Clocks 58 9.1.7 When is Synchronization establis

Distributed Clocks I-60 Slave Controller – Technology 9.2 SyncSignals and LatchSignals ESCs with Distributed Clocks support generation of SyncS

Distributed Clocks Slave Controller – Technology I-61 9.2.3 SyncSignal Generation The DC Cyclic Unit / Sync Unit supports the generation of a ba

Distributed Clocks I-62 Slave Controller – Technology The registers used for SyncSignal Generation are shown in Table 33. Table 33: Registers for

Distributed Clocks Slave Controller – Technology I-63 9.2.3.5 SYNC1 Generation The second SyncSignal (SYNC1) depends on SYNC0, it can be generat

Distributed Clocks I-64 Slave Controller – Technology 9.2.3.6 SyncSignal Initialization Example The SyncSignal generation is initialized with th

Distributed Clocks Slave Controller – Technology I-65 The registers used for LatchSignal event time stamping are shown in Table 34: Table 34: Reg

Distributed Clocks I-66 Slave Controller – Technology 9.3 System Time PDI Controlled Sometimes Distributed Clocks of different EtherCAT networks

Distributed Clocks Slave Controller – Technology I-67 The second option uses a SyncSignal output of ESC 1 to trigger Latch0 at ESC 2 and an inter

Distributed Clocks I-68 Slave Controller – Technology 9.4 Communication Timing Three communication modes are possible: 1. Free Run EtherCAT Com

Distributed Clocks Slave Controller – Technology I-69 Cycle Time Jitter Cycle Time Jitter is application-specific and depends on the jitter of th

CONTENTS Slave Controller – Technology I-IX 15.2 ERR LED 88 15.2.1 ERR LED override 88 15.3 STATE LED and STATE_RUN LED Signal 89 15.4 LIN

EtherCAT State Machine I-70 Slave Controller – Technology 10 EtherCAT State Machine The EtherCAT State machine (ESM) is responsible for the coor

EtherCAT State Machine Slave Controller – Technology I-71 10.1 EtherCAT State Machine Registers The state machine is controlled and monitored vi

SII EEPROM I-72 Slave Controller – Technology 11 SII EEPROM EtherCAT slave controllers use a mandatory NVRAM (typically a serial EEPROM with I²C

SII EEPROM Slave Controller – Technology I-73 11.1 SII EEPROM Content The ESC Configuration Area (EEPROM word addresses 0 to 7) is automatically

SII EEPROM I-74 Slave Controller – Technology An excerpt of the SII EEPROM content following the ESC Configuration area is shown in Table 38. For

SII EEPROM Slave Controller – Technology I-75 11.2.1 SII EEPROM Errors The ESC retries reading the EEPROM after power-on or reset once if an err

SII EEPROM I-76 Slave Controller – Technology 11.2.1.1 Missing Acknowledge Missing acknowledges from the EEPROM chip are a common issue, especia

SII EEPROM Slave Controller – Technology I-77 11.2.3 Read/Write/Reload Example The following steps have to be performed for an SII EEPROM read o

SII EEPROM I-78 Slave Controller – Technology 11.3 SII EEPROM Electrical Interface (I2C) The SII EEPROM Interface is intended to be a point-to-p

SII EEPROM Slave Controller – Technology I-79 11.3.3 I²C Access Protocol Each EEPROM access begins with a Start condition and ends with a Stop c