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ABBREVIATIONS
I-XVI Slave Controller – Technology
ISO/OSI Model
ISO Open Systems Interconnection Basic Reference Model (ISO 7498):
describes the division of communication into 7 layers.
IT
Information Technology: Devices and methods required for computer-aided
information processing.
LatchSignal
Signal for Distributed Clocks time stamping
LED
Light Emitting Diode, used as an indicator
Link/Act
Link/Activity Indicator (LED)
Little Endian
Data format (also Intel format). The less significant byte is transferred first when
a word is transferred. With EtherCAT, the least significant bit is the first on the
wire.
LLDP
Lower Layer Discovery Protocol – provides the basis for topology discovery and
configuration definition (see IEEE802.1ab)
LRD
Logical Read
LWR
Logical Write
LRW
Logical ReadWrite
LVDS
Low Voltage Differential Signaling
M12
Connector used for industrial Ethernet
MAC
Media Access Control: Specifies station access to a communication medium.
With full duplex Ethernet, any station can send data at any time; the order of
access and the response to overload are defined at the network component
level (switches).
MAC Address
Media Access Control Address: Also known as Ethernet address; used to
identify an Ethernet node. The Ethernet address is 6 bytes long and is assigned
by the IEEE.
Mandatory
Services
Mandatory services, parameters, objects, or attributes. These must be
implemented by every station.
MBX
Mailbox
MDI
Media Dependent Interface:
Use of connector Pins and Signaling (PC side)
MDI-X
Media Dependent Interface (crossed):
Use of connector Pins and Signaling with crossed lines (Switch/hub side)
MI
(PHY) Management Interface
MII
Media Independent Interface: Standardized interface between the Ethernet
MAC and PHY.
Multicast
Transmission to multiple destination stations with a frame – generally uses a
special address.
NOP
No Operation
NVRAM
Non-volatile random access memory, e.g. EEPROM or Flash.
Octet
Term from IEC 61158 – one octet comprises exactly 8 bits.
OP
Operational state of EtherCAT state machine
- DOCUMENT HISTORY 5
- TABLES 11
- Table 1: ESC Main Features 21
- 2 EtherCAT Protocol 24
- Figure 3: EtherCAT Datagram 25
- Table 3: EtherCAT Datagram 26
- EtherCAT Protocol 29
- 2.5 EtherCAT Command Types 29
- 3 Frame Processing 32
- EtherCAT 34
- Slave Controller 34
- Figure 6: Circulating Frames 35
- 5 Ethernet Physical Layer 40
- Configuration 43
- PHY address 47
- Figure 8: Write access 49
- Figure 9: Read access 49
- Ethernet PHY 50
- > 1mm gap between 51
- PE and Virtual Ground 51
- Figure 12: RJ45 Connector 52
- Standard Ethernet 54
- MAC (µC/FPGA) 54
- 6 EBUS/LVDS Physical Layer 55
- 7 FMMU 59
- Logical Address Space 60
- Physical Address Space 60
- 8 SyncManager 61
- Channel 64
- Master µController 66
- 9 Distributed Clocks 67
- Drift compensation 69
- Distributed Clocks 72
- Local time 76
- Propagation delay 76
- Received System Time 76
- 0x0920:0x0927 77
- SYNC0 Cycle Time 81
- Start Time 81
- Pulse Length of 81
- SyncSignals 81
- ESC 1 generates SyncPulse 87
- (calculated by µC) to System 87
- Time register of ESC 2 87
- 10 EtherCAT State Machine 90
- 11 SII EEPROM 92
- 0x5:0x6 94
- 0x8:0x9 94
- EEPROM_SIZE 98
- Table 43: I²C Control Byte 99
- Table 44: I²C Write Access 99
- EEPROM_CLK 100
- EEPROM_DATA 100
- 12 Interrupts 102
- (0x0210:0x0211) 103
- (0x0200:0x0201) 103
- 13 Watchdogs 104
- 14 Error Counters 105
- 15 LED Signals (Indicators) 107
- Table 56: LINKACT LED States 109
- 17 Additional Information 114
- 18 Appendix 116
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