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ABBREVIATIONS
Slave Controller – Technology I-XIII
ABBREVIATIONS
µC
Microcontroller
ADR
Address
ADS
Automation Device Specification (Beckhoff)
AL
Application Layer
AMBA
®
Advanced Microcontroller Bus Architecture from ARM
®
APRD
Auto Increment Physical Read
APWR
Auto Increment Physical Write
APRW
Auto Increment Physical ReadWrite
ARMW
Auto Increment Physical Read Multiple Write
AoE
ADS over EtherCAT
ASIC
Application Specific Integrated Chip
Auto Crossover
Automatic detection of whether or not the send and receive lines are crossed.
Auto Negotiation
Automatic negotiation of transmission speeds between two stations.
Avalon
®
On-chip bus for Altera
®
FPGAs
AXI
TM
Advanced eXtensible Interface Bus, an AMBA interconnect. Used as On-Chip-
bus
Big Endian
Data format (also Motorola format). The more significant byte is transferred first
when a word is transferred. However, for EtherCAT the least significant bit is
the first on the wire.
BOOT
BOOT state of EtherCAT state machine
Boundary Clock
A station that is synchronized by another station and then passes this
information on.
Bridge
A term for switches used in standards. Bridges are devices that pass on
messages based on address information.
Broadcast
An unacknowledged transmission to an unspecified number of receivers.
BRD
Broadcast Read
BWR
Broadcast Write
BRW
Broadcast ReadWrite
Cat
Category – classification for cables that is also used in Ethernet. Cat 5 is the
minimum required category for EtherCAT. However, Cat 6 and Cat 7 cables are
available.
CoE
CAN
®
application layer over EtherCAT
Communication
Stack
A communication software package that is generally divided into successive
layers, which is why it is referred to as a stack.
Confirmed
Means that the initiator of a service receives a response.
CRC
Cyclic Redundancy Check, used for FCS
- DOCUMENT HISTORY 5
- TABLES 11
- Table 1: ESC Main Features 21
- 2 EtherCAT Protocol 24
- Figure 3: EtherCAT Datagram 25
- Table 3: EtherCAT Datagram 26
- EtherCAT Protocol 29
- 2.5 EtherCAT Command Types 29
- 3 Frame Processing 32
- EtherCAT 34
- Slave Controller 34
- Figure 6: Circulating Frames 35
- 5 Ethernet Physical Layer 40
- Configuration 43
- PHY address 47
- Figure 8: Write access 49
- Figure 9: Read access 49
- Ethernet PHY 50
- > 1mm gap between 51
- PE and Virtual Ground 51
- Figure 12: RJ45 Connector 52
- Standard Ethernet 54
- MAC (µC/FPGA) 54
- 6 EBUS/LVDS Physical Layer 55
- 7 FMMU 59
- Logical Address Space 60
- Physical Address Space 60
- 8 SyncManager 61
- Channel 64
- Master µController 66
- 9 Distributed Clocks 67
- Drift compensation 69
- Distributed Clocks 72
- Local time 76
- Propagation delay 76
- Received System Time 76
- 0x0920:0x0927 77
- SYNC0 Cycle Time 81
- Start Time 81
- Pulse Length of 81
- SyncSignals 81
- ESC 1 generates SyncPulse 87
- (calculated by µC) to System 87
- Time register of ESC 2 87
- 10 EtherCAT State Machine 90
- 11 SII EEPROM 92
- 0x5:0x6 94
- 0x8:0x9 94
- EEPROM_SIZE 98
- Table 43: I²C Control Byte 99
- Table 44: I²C Write Access 99
- EEPROM_CLK 100
- EEPROM_DATA 100
- 12 Interrupts 102
- (0x0210:0x0211) 103
- (0x0200:0x0201) 103
- 13 Watchdogs 104
- 14 Error Counters 105
- 15 LED Signals (Indicators) 107
- Table 56: LINKACT LED States 109
- 17 Additional Information 114
- 18 Appendix 116
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