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ABBREVIATIONS
I-XIV Slave Controller – Technology
Cut Through
Procedure for cutting directly through an Ethernet frame by a switch before the
complete message is received.
Cycle
Cycle in which data is to be exchanged in a system operating on a periodical
basis.
DC
Distributed Clocks
Mechanism to synchronize EtherCAT slaves and master
Delay
Delays can be caused by run-times during transfer or internal delays of a
network component.
Dest Addr
Destination address of a message (the destination can be an individual network
station or a group (multicast).
DHCP
Dynamic Host Configuration Protocol, used to assign IP addresses (and other
important startup parameter in the Internet context).
DL
Data Link Layer, also known as Layer 2. EtherCAT uses the Data Link Layer of
Ethernet, which is standardized as IEEE 802.3.
DNS
Domain Name Service, a protocol for domain name to IP addresses resolution.
EBUS
Based on LVDS (Low Voltage Differential Signaling) standard specified in
ANSI/TIA/EIA-644-1995
ECAT
EtherCAT
EEPROM
Electrically Erasable Programmable Read Only Memory. Non-volatile memory
used to store EtherCAT Slave Information (ESI). Connected to the SII.
EMC
Electromagnetic Compatibility, describes the robustness of a device with regard
to electrical interference from the environment.
EMI
Electromagnetic Interference
Engineering
Here: All applications required to configure and program a machine.
EoE
Ethernet over EtherCAT
EOF
End of Frame
ERR
Error indicator for AL state
Err(x)
Physical Layer RX Error LED for debugging purposes
ESC
EtherCAT Slave Controller
ESI
EtherCAT Slave Information, stored in SII EEPROM
ESM
EtherCAT State Machine
ETG
EtherCAT Technology Group (http://www.ethercat.org)
EtherCAT
Real-time Standard for Industrial Ethernet Control Automation Technology
(Ethernet for Control Automation Technology)
EtherType
Identification of an Ethernet frame with a 16-bit number assigned by IEEE. For
example, IP uses EtherType 0x0800 (hexadecimal) and the EtherCAT protocol
uses 0x88A4.
- DOCUMENT HISTORY 5
- TABLES 11
- Table 1: ESC Main Features 21
- 2 EtherCAT Protocol 24
- Figure 3: EtherCAT Datagram 25
- Table 3: EtherCAT Datagram 26
- EtherCAT Protocol 29
- 2.5 EtherCAT Command Types 29
- 3 Frame Processing 32
- EtherCAT 34
- Slave Controller 34
- Figure 6: Circulating Frames 35
- 5 Ethernet Physical Layer 40
- Configuration 43
- PHY address 47
- Figure 8: Write access 49
- Figure 9: Read access 49
- Ethernet PHY 50
- > 1mm gap between 51
- PE and Virtual Ground 51
- Figure 12: RJ45 Connector 52
- Standard Ethernet 54
- MAC (µC/FPGA) 54
- 6 EBUS/LVDS Physical Layer 55
- 7 FMMU 59
- Logical Address Space 60
- Physical Address Space 60
- 8 SyncManager 61
- Channel 64
- Master µController 66
- 9 Distributed Clocks 67
- Drift compensation 69
- Distributed Clocks 72
- Local time 76
- Propagation delay 76
- Received System Time 76
- 0x0920:0x0927 77
- SYNC0 Cycle Time 81
- Start Time 81
- Pulse Length of 81
- SyncSignals 81
- ESC 1 generates SyncPulse 87
- (calculated by µC) to System 87
- Time register of ESC 2 87
- 10 EtherCAT State Machine 90
- 11 SII EEPROM 92
- 0x5:0x6 94
- 0x8:0x9 94
- EEPROM_SIZE 98
- Table 43: I²C Control Byte 99
- Table 44: I²C Write Access 99
- EEPROM_CLK 100
- EEPROM_DATA 100
- 12 Interrupts 102
- (0x0210:0x0211) 103
- (0x0200:0x0201) 103
- 13 Watchdogs 104
- 14 Error Counters 105
- 15 LED Signals (Indicators) 107
- Table 56: LINKACT LED States 109
- 17 Additional Information 114
- 18 Appendix 116
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