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Distributed Clocks
Slave Controller – Technology I-49
9.1.1 Clock Synchronization Process
The clock synchronization process consists of three steps:
1. Propagation Delay Measurement:
The master initiates propagation delay measurement between all slaves in all directions. Each
EtherCAT slave controller measures the receive time of the measurement frame. The master
collects the time stamps afterwards and calculates the propagation delays between all slaves.
2. Offset compensation to Reference Clock (System Time):
The local time of each slave clock is compared to the System Time. The difference is
compensated individually by writing it to each slave. All devices get the same absolute System
Time.
3. Resetting the Time Control Loop:
The current filter status needs to be reset to eliminate influences of previous measurements and
improve repeatability.
4. Drift compensation to Reference Clock:
The drift between Reference Clock and local clock has to be compensated by regularly measuring
the differences and readjusting the local clocks.
The following figure illustrates the compensation calculations for two cases, in the first case the
System Time is less than the slave’s local time, in the second case, it is the other way around.
Reference
Clock
Slave Clock
t
System Time
t
Local time
Drift compensation frame
carrying current System Time
TX
Propagation delay compensation
Offset compensation
Drift compensation
Reference
Clock
Slave Clock
t
System Time
t
Local Time
Drift compensation frame
carrying current System Time
TX
Propagation delay compensation
Offset compensation
RX
Drift compensation
RX
Goal: Slave clock has
copy of System Time
System Time < Local Time
System Time > Local Time
Propagation delay
Propagation delay
System Time
Local time
System Time
Local time
Goal: Slave clock has
copy of System Time
x
x
Figure 27: Propagation Delay, Offset, and Drift Compensation
- DOCUMENT HISTORY 5
- TABLES 11
- Table 1: ESC Main Features 21
- 2 EtherCAT Protocol 24
- Figure 3: EtherCAT Datagram 25
- Table 3: EtherCAT Datagram 26
- EtherCAT Protocol 29
- 2.5 EtherCAT Command Types 29
- 3 Frame Processing 32
- EtherCAT 34
- Slave Controller 34
- Figure 6: Circulating Frames 35
- 5 Ethernet Physical Layer 40
- Configuration 43
- PHY address 47
- Figure 8: Write access 49
- Figure 9: Read access 49
- Ethernet PHY 50
- > 1mm gap between 51
- PE and Virtual Ground 51
- Figure 12: RJ45 Connector 52
- Standard Ethernet 54
- MAC (µC/FPGA) 54
- 6 EBUS/LVDS Physical Layer 55
- 7 FMMU 59
- Logical Address Space 60
- Physical Address Space 60
- 8 SyncManager 61
- Channel 64
- Master µController 66
- 9 Distributed Clocks 67
- Drift compensation 69
- Distributed Clocks 72
- Local time 76
- Propagation delay 76
- Received System Time 76
- 0x0920:0x0927 77
- SYNC0 Cycle Time 81
- Start Time 81
- Pulse Length of 81
- SyncSignals 81
- ESC 1 generates SyncPulse 87
- (calculated by µC) to System 87
- Time register of ESC 2 87
- 10 EtherCAT State Machine 90
- 11 SII EEPROM 92
- 0x5:0x6 94
- 0x8:0x9 94
- EEPROM_SIZE 98
- Table 43: I²C Control Byte 99
- Table 44: I²C Write Access 99
- EEPROM_CLK 100
- EEPROM_DATA 100
- 12 Interrupts 102
- (0x0210:0x0211) 103
- (0x0200:0x0201) 103
- 13 Watchdogs 104
- 14 Error Counters 105
- 15 LED Signals (Indicators) 107
- Table 56: LINKACT LED States 109
- 17 Additional Information 114
- 18 Appendix 116
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