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SII EEPROM
I-74 Slave Controller – Technology
An excerpt of the SII EEPROM content following the ESC Configuration area is shown in Table 38.
For more information, refer to the ETG.2000 EtherCAT Slave Information (ESI) Specification, available
from the download section of the EtherCAT Technology Group website (http://www.ethercat.org).
Table 38: SII EEPROM Content Excerpt
Word
Address
Parameter
Word
Address
Parameter
0x0
PDI Control
0x14
Bootstrap Receive Mailbox Offset
0x1
PDI Configuration
0x15
Bootstrap Receive Mailbox Size
0x2
Pulse Length of SYNC Signals
0x16
Bootstrap Send Mailbox Offset
0x3
Extended PDI Configuration
0x17
Bootstrap Send Mailbox Size
0x4
Configured Station Alias
0x18
Standard Receive Mailbox Offset
0x5:0x6
Reserved
0x19
Standard Receive Mailbox Size
0x7
Checksum
0x1A
Standard Send Mailbox Offset
0x8:0x9
Vendor ID
0x1B
Standard Send Mailbox Size
0xA:0xB
Product Code
0x1C
Mailbox Protocol
0xC:0xD
Revision Number
0x1D:0x3D
Reserved
0xE:0xF
Serial Number
0x3E
Size
0x10
Execution Delay
0x3F
Version
0x11
Port0 Delay
0x40
First Category Type/Vendor
Specific
0x12
Port1 Delay
0x41
Following Category Word Size
0x13
Reserved
0x42
Category Data
…
Second Category …
11.2 SII EEPROM Logical Interface
The SII EEPROM interface of the ESC is either controlled by EtherCAT or by the PDI. Initially,
EtherCAT has EEPROM interface access, but it can transfer access to the PDI.
Table 39: SII EEPROM Interface Register Overview
Register Address
Description
0x0500
EEPROM Configuration
0x0501
EEPROM PDI Access State
0x0502:0x0503
EEPROM Control/Status
0x0504:0x0507
EEPROM Address
0x0508:0x050F
EEPROM Data
The EEPROM interface supports three commands: write to one EEPROM address (1 Word), read
from EEPROM (2 or 4 Words, depending on ESC), or reload ESC configuration from EEPROM.
- DOCUMENT HISTORY 5
- TABLES 11
- Table 1: ESC Main Features 21
- 2 EtherCAT Protocol 24
- Figure 3: EtherCAT Datagram 25
- Table 3: EtherCAT Datagram 26
- EtherCAT Protocol 29
- 2.5 EtherCAT Command Types 29
- 3 Frame Processing 32
- EtherCAT 34
- Slave Controller 34
- Figure 6: Circulating Frames 35
- 5 Ethernet Physical Layer 40
- Configuration 43
- PHY address 47
- Figure 8: Write access 49
- Figure 9: Read access 49
- Ethernet PHY 50
- > 1mm gap between 51
- PE and Virtual Ground 51
- Figure 12: RJ45 Connector 52
- Standard Ethernet 54
- MAC (µC/FPGA) 54
- 6 EBUS/LVDS Physical Layer 55
- 7 FMMU 59
- Logical Address Space 60
- Physical Address Space 60
- 8 SyncManager 61
- Channel 64
- Master µController 66
- 9 Distributed Clocks 67
- Drift compensation 69
- Distributed Clocks 72
- Local time 76
- Propagation delay 76
- Received System Time 76
- 0x0920:0x0927 77
- SYNC0 Cycle Time 81
- Start Time 81
- Pulse Length of 81
- SyncSignals 81
- ESC 1 generates SyncPulse 87
- (calculated by µC) to System 87
- Time register of ESC 2 87
- 10 EtherCAT State Machine 90
- 11 SII EEPROM 92
- 0x5:0x6 94
- 0x8:0x9 94
- EEPROM_SIZE 98
- Table 43: I²C Control Byte 99
- Table 44: I²C Write Access 99
- EEPROM_CLK 100
- EEPROM_DATA 100
- 12 Interrupts 102
- (0x0210:0x0211) 103
- (0x0200:0x0201) 103
- 13 Watchdogs 104
- 14 Error Counters 105
- 15 LED Signals (Indicators) 107
- Table 56: LINKACT LED States 109
- 17 Additional Information 114
- 18 Appendix 116
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