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EtherCAT State Machine
Slave Controller – Technology I-71
10.1 EtherCAT State Machine Registers
The state machine is controlled and monitored via registers within the ESC. The master requests state
changes by writing to the AL Control register. The slave indicates its state in the AL Status register
and puts error codes into the AL Status Code register.
Table 35: Registers for the EtherCAT State Machine
Register Address
Name
Description
0x0120:0x0121
AL Control
Requested state by the master
0x0130:0x0131
AL Status
AL Status of the slave application
0x0134:0x0135
AL Status Code
Error codes from the slave application
0x0141[0]
ESC Configuration
Device emulation configuration
NOTE: The PDI Control register is set via SII EEPROM/IP Core configuration, other registers might not be
available in specific ESCs. Refer to Section II and Section III for details.
10.1.1 AL Control and AL Status Register
Writing the AL Control register (0x0120:0x0121) initiates a state transition of the device state machine.
The AL Status register (0x0130:0x0131) reflects the current state of the slave.
Table 36: AL Control and AL Status Register Values
Register [3:0]
AL Control Register 0x0120
AL Status Register 0x0130
1
Request Init state
Init state
3
Request Bootstrap state (optional)
Bootstrap state (optional)
2
Request Pre-Operational state
Pre-Operational state
4
Request SAFE-Operational state
SAFE-Operational state
8
Request Operational state
Operational state
10.1.2 Device Emulation
Simple devices (without µController) have the device emulation enabled (0x0141[0]=1). The AL
Control register is directly copied into the AL Status register by the ESC. The master should not set
the Error Indication Acknowledge bit for such slaves at all, because setting this bit would result in
setting the Error Indication bit – although no error occurred.
10.1.3 Error Indication and AL Status Code Register
The slave indicates errors during a state transition by setting the Error Indication flag (0x0130[4]=1)
and writing an error description into the AL Status Code register (0x0134:0x0135). The master
acknowledges the Error Indication flag of the slave by setting the Error Indication Acknowledge flag
(0x0120[4]).
For more information on defined AL Status Codes, refer to the EtherCAT Knowledge Base available at
the EtherCAT Technology Group website (http://www.ethercat.org, Guidelines and Protocol
Enhancements).
- DOCUMENT HISTORY 5
- TABLES 11
- Table 1: ESC Main Features 21
- 2 EtherCAT Protocol 24
- Figure 3: EtherCAT Datagram 25
- Table 3: EtherCAT Datagram 26
- EtherCAT Protocol 29
- 2.5 EtherCAT Command Types 29
- 3 Frame Processing 32
- EtherCAT 34
- Slave Controller 34
- Figure 6: Circulating Frames 35
- 5 Ethernet Physical Layer 40
- Configuration 43
- PHY address 47
- Figure 8: Write access 49
- Figure 9: Read access 49
- Ethernet PHY 50
- > 1mm gap between 51
- PE and Virtual Ground 51
- Figure 12: RJ45 Connector 52
- Standard Ethernet 54
- MAC (µC/FPGA) 54
- 6 EBUS/LVDS Physical Layer 55
- 7 FMMU 59
- Logical Address Space 60
- Physical Address Space 60
- 8 SyncManager 61
- Channel 64
- Master µController 66
- 9 Distributed Clocks 67
- Drift compensation 69
- Distributed Clocks 72
- Local time 76
- Propagation delay 76
- Received System Time 76
- 0x0920:0x0927 77
- SYNC0 Cycle Time 81
- Start Time 81
- Pulse Length of 81
- SyncSignals 81
- ESC 1 generates SyncPulse 87
- (calculated by µC) to System 87
- Time register of ESC 2 87
- 10 EtherCAT State Machine 90
- 11 SII EEPROM 92
- 0x5:0x6 94
- 0x8:0x9 94
- EEPROM_SIZE 98
- Table 43: I²C Control Byte 99
- Table 44: I²C Write Access 99
- EEPROM_CLK 100
- EEPROM_DATA 100
- 12 Interrupts 102
- (0x0210:0x0211) 103
- (0x0200:0x0201) 103
- 13 Watchdogs 104
- 14 Error Counters 105
- 15 LED Signals (Indicators) 107
- Table 56: LINKACT LED States 109
- 17 Additional Information 114
- 18 Appendix 116
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