Beckhoff EtherCAT Technology Section I Bedienungsanleitung PDF herunterladen (Seite 98)

SII EEPROM

I-78 Slave Controller – Technology

11.3 SII EEPROM Electrical Interface (I

The SII EEPROM Interface is intended to be a point-to-point interface between the ESC and the I²C

EEPROM. If other I²C masters are required to access the I²C bus, the ESC must be held in reset state

(e.g. for in-circuit-programming of the EEPROM), otherwise access collisions are possible.

The SII EEPROM interface has the following signals

EtherCAT

device

EEPROM_DATA

EEPROM_CLK

EEPROM_SIZE

Figure 37: I²C EEPROM signals

Table 41: I²C EEPROM signals

Signal

Direction

Description

EEPROM_CLK

OUT

I²C clock

EEPROM_DATA

BIDIR

I²C data

EEPROM_SIZE

EEPROM size configuration

Both EEPROM_CLK and EEPROM_DATA must have a pull-up resistor (4.7 kΩ recommended for

ESCs), either integrated into the ESC or connected externally.

11.3.1 Addressing

EtherCAT and ESCs use word addressing when accessing the EEPROM, although the I²C interface

actually uses byte addressing. The lowest address bit A[0] is added internally by the EEPROM

interface controller of the ESCs. I.e., the EEPROM address register (0x0504:0x0507) reflects the

physical EEPROM address bits A[18:1] (higher address bits are reserved/are zero).

SII EEPROM word 0 is located at I²C address 0, i.e., the I²C device address has to be set to 0.

11.3.2 EEPROM Size

Depending on the EEPROM size, one out of two EEPROM algorithms has to be selected with the

EEPROM_SIZE configuration signal. Smaller EEPROMs need only one address byte, larger ones

need two address bytes:

Table 42: EEPROM Size

EEPROM Size

Address Bytes

Max. I²C Address Bits

EEPROM_SIZE signal

1 Kbit – 16 Kbit

32 Kbit – 4 Mbit

The availability of the EEPROM signals as well as their names depend on the specific ESC.

1 2 ... 93 94 95 96 97 98 99 100 101 102 103 ... 115 116

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